Razlaga timingov pri ramih...

Precharge to Activate Latency: This setting relates to the rows in DDR. This setting deals with the delay between two states, the activate and precharge. Lowering it also improves performance.

RAS to CAS Latency: This setting controls the delay between the RAS command and the CAS command. Once again, lower is better.

CAS Latency: This term is otherwise known as Column Access Strobe delay. DDR ram can be described with columns and rows. A "strobe" is what finds the correct column or row of data. Therefore, the CAS latency is the delay between the chipset read command, and the time that the data becomes available. Lower is better!

RAS Precharge Latency: This last setting controls the number of idle clocks after issuing a precharge command.

Najbolj je važna CAS latency,čim bolj nižje je bolj hitri so rami