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Ideja za hardcore modifikacijo oz. Ko ima človek preveč časa!

Ideja za hardcore modifikacijo oz. Ko ima človek preveč časa!

TribesMan ::

Ker mi ni jasno kam bi podturil to vprašanje sem ga kar tukej postal, če komu lokacija ne odgovarja naj ga premakne.

Zadeva se vrti okoli generatorja ure na osnovni plošči. Zadnjič sem malce raziskoval plato in mal gledal kaj bi se dal modificirat. Ustavil sem se pri generatorju ure, ko sem z neta zdownloadal datasheet in se malce poglobil v zadevo sem ugotovil, da ta generator ne samo da določa FSB ampak ima tudi ločene izhode za PCI AGP RAM USB... Zdej me pa zanima glede na to, da je plata še na starem BX chipsetu, kakšna neumnost bi bila če bi se lotil narediti zadevo, da bi sam po želji in neglede na razne deljitelje določal frekvenco posameznih vodil AGP, PCI... Ali je pri starejših chipsetih nujno da so vse frekvence v točno določenih razmerjih (Recimo AGP/FSB=2/3)? Ali pa to ni nujno in bi lahko recimo naredil zadevo, da bi recimo nastavil fiksne frekvence za AGP=66MHz, PCI=33MHz, USB=48MHz. Za hitrost rama in FSBja pa bi naredil drugačno zadevo s pomočjo katere, bi potem nastavil vsako od teh hitrosti na čimvečjo možno (Recimo tako da bi RAM stalno deloval na največji mogoči frekvenci recimo 140MHz, procesor pa na taki, da bi bil sistem še vedno stabilen recimo 125MHz.) Ali bi to lahko povzročilo kakšne hude preglavice, ker potem razmerja med vodilom in ostalimi zadevami ne bi bila več točno določena ampak bi bila toliko kakor bi meni odgovarjalo.
Sej če tako pogledaš recimo AGP in FSB sta že tako v enem glupem razmerju 2:3 tak da itaq mora FSB "čakati" na podatke z AGPja (To je sam moja teorija!!!) in mu je itaq vseen al čaka 3/2 takta al pa 0.563487 takta.

Zdej neki sm že pred leti zasledil (ko so bli še celeroni 300A aktualni), da so neki japončki naredili zadevo (v sebi je imela vgrajen pravi mali OS, preko katerega so se odvijale vse nastavitve, gor pa je bil še LCD da si videl kaj štelaš), ki so jo na plato pricinili prek kablovja na clock generator (oziroma namesto njega) potem pa so nastavili vsako frekvenco neodvisno eno od druge. Zadeva je delovala v korakih po 1kHz (wiii!!), lahko pa si spreminjal frekvence tudi med delovanjem računalnika (prosm ne se smejat, tako je tam pisal). Zadevco so takrat tud prodajal ampk je koštala mastne denarce. Zrevn si tud dobil načrte kako zadevo piciniti na plato za nekaj takrat aktualnih plat.....Narejeno pa je bilo vseskupaj okoli nastavljivih PLL zank in schmittovih triggerjev.

Torej kaj mislite. Vem da je idej čist mim ampk jest bi kr probal naredit neki tazga (plate mi ni škoda, cajt bo po izpitih, mam tud kr nekaj elekto izkušenj tak da naredit kej tazga sam po seb ne bi bil problem). Problem je le če bi zadeva zagotovo delovala.

LP

TribesMan

P.S.: Take neumnosti pač premišljam ko ne morem spat.

P.P.S.: Zdnje cajte ne morem nič spat.
Moj kompjuter dela: KVIIIIK ... KVIIIK ... KVIIIK.

Ko ga navijem dela: KVIKKVIKKIVKKVIK. :)

OwcA ::

Tole bi morda bilo vredno ogleda, saj je nekaj podobnega, kot je imel japonček, ki ga omenjaš (na Japonskem se stvari reče TurboPLL), a ta stvar le premosti omejitve vgrajenega PLLja, delitelji pa ostanejo nespremenjeni.
S spreminjanjem teh, pa za enkrat niso imeli veliko sreče, sam sem zasledil samo eno stran (pa še ta je v japonščini), kjer je takšna modifikacijo opisana, ki pa žal ni več dostopna. Bom poiskal, če še imam na disku, in objavil tukaj.

Zgodovina sprememb…

  • spremenilo: OwcA ()

OwcA ::

Našel (prekopirano iz strani http://www.din.or.jp/~kzo/pc/pcup/bh6/b..., prevedeno z BabelFishom):

-------------------

* Background

The article of PCI asynchronous remodelling to be run a special edition by the magazine, 1999 Vol.1 No3 of the separate DOS/V magazine CUSTOM, because exactly material was the BH6 Ver1.1, if you remodel in the same way to also the BH6 Ver1.01 of this one possession, those where you thought whether it does not mean that setting of the FSB133mHz is useful are the remodelling reason. Especially, setting of the FSB124,133, was the kind of setting which does not form the meaning only 1/3 supplying in the PCI, for the BH6 Ver1.01.

Being the AGP also you remodel to be simultaneously asynchronously,, but because it seems that is trouble depending upon the type of VIDEO card, made just the PCI.

Furthermore, the magazine the chestnut of the writer HP of palm has become with this way.

At the time of this remodelling, it becomes all self responsibilities. Especially because the latest remodelling seems that degree of hardness differs with the M/B, please note.



- Crystal oscillograph (option)

As for the crystal oscillograph the 33.3mHz which is supplied to the PCI is the basis, but the over clock (the O/C) because the PCI is not linked to the CPU clock the time, the case where the O/C was executed, decrease of performance is expected. In other words when we would like to put the PCI in O/C state, it means to select the crystal oscillograph the around the 36mHz - the 39mHz at the time of selecting the original 々. Because this selection is supplied usual, it is thought the one which is considered well is safe. Sigma (The ^^) remodelling has selected the 33.3mHz of the basis by the way.

- 0.1 mu F ceramic condensers

- TTL IC 74AS04 (IC under picture)

* Motherboard (M/B) in remodelling place being attached

You think we would like to verify the remodelling place of M/B side, at the time of remodelling. PLL IC of the BH6 Ver1.01 has adopted the W124G of the IC WORKS.



Regrettable there is no Datasheet of the W124G. (^o^; Those where it is adopted for present BH6 1.1 become the W196G. The W196G has become the W124G and pin compatible. When you look at the Datasheet of the Cypress, because the W196G in 1999/11/29 point in time seems that is not, we have decided to refer the Datasheet of the W196.



The above-mentioned picture does being something which shows the pin which is necessary for PCI asynchronous remodelling from the Datasheet of the W196. Because the Datasheet itself is a copyright of enterprise, being something which I made, it does. Furthermore when the actual picture you try collating, below being connected to 4 - 8, 10 - 11 pins of PLL IC of the W196, resistance is taken, the PCI output which has been formed with PLL IC is divided. It means to fill the output from the crystal oscillograph to the pad the side which the arrow points. (Total 7 place)



* Processing the crystal oscillograph side

It processes crystal oscillograph side.

- You bend 1,3,5,9,11,13 pins of the 74AS04 to the center and wire.

- 0.1 mu F ceramic condensers & are installed in 7 14 pins of the crystal oscillograph of the 33.3mHz. It cuts 1 pin.



When above-mentioned job ends, we wire the 74AS04 and the crystal oscillograph. It is the kind of image which adds the 74AS04 between the pin of the crystal oscillograph.

7,8,14 pins of the crystal oscillograph are connected to 7,9,14 pins of the 74AS04. (Pin of blue color and green color reference)



* Wiring

* Crystal oscillograph side and wiring of resistance

Wiring of the M/B and crystal oscillograph side those of the magazine wired with the method of differing. It is the system where contents of the magazine take resistance, acquire resistance for the second time on the pad side which is filled and wire. (Chestnut HP reference of palm)

As for the method I doing in one time universal baseplate resistance and crystal oscillograph side it is the method of wiring, furthermore filling to M/B side. When you say, it selected the method why of differing because the pad of M/B side is very brittle, when little pressure is imposed, every pad in order to prevent the fact that you take is.

At the time of the nuclear takeover which has gone usually when the pad takes, mostly it is less crowded and being to be a pad, it does, but it is less crowded in the PCI of the BH6 and there is no pad. Following, there are various methods with being you think, it does, but we think whether it does not mean that also the method I doing becomes reference.



The above-mentioned picture is wiring of the 74AS04 and resistance. We wire 2.4,6,8,10,12 pins of the 74AS04 with resistance. Because, as for resistance 7 it is, it becomes the shape which is distributed from the pin of somewhere. In case of me we do two wiring from 8 pins.

* M/B side and wiring of resistance

Those which are modularized in shape of the above-mentioned picture we wire in the M/B.



The picture which it expands is below. The ジュンフロン line where the picture the right is red wires in +5v. (14 pins of 74AS04)





* Wiring of electrical power system

- +5v power source of the side crystal oscillograph wires in order to be able to supply from +5v. We wired in 14 pins of the 74AS04 and the TTL IC nearby pad of the M/B.



- Wiring of the GND side GND 7 pins of the 74AS04 and the R10 of the M/B wired on GND side of the being less crowded pad which is written. (Black ジュンフロン line)



* Verification

When remodelling ends, continuity check between the pad is done first with the tester. When continuity check is completed, being to enter into operation verification, it does, but the one which as for the important part is avoided suddenly is safe. We check operation whether at the standard clock the chitin it works.

In case of me you used the old P2-333, at the WCPUID verification after doing, the P2-350 (the SL38M) you were similar and verified. In order to verify whether actually remodelling has succeeded, the VIDEO CARD of the N/B which is procured rather in the past was used. The VirgecDx is loaded onto this VIDEO CARD.

At the BIOS it sets to the V-Core2.3v, the FSB133 (1/3) selects. Actually when it is non remodelling, because the 133mHz 1/3 is, it is not the setting which the PCI is supplied, can use the 44.3mHz very.

When it starts promptly, you stand up safely. Also the in a general way BENCH was all right.



* Thought and thanks

As for the BH6 the between the CPU and the MEMORY it is the M/B which very it is easy to handle widely. But is not the one where from the flow of recent high FSB conversion it have put away in the closet to be more, probably will be? You knew that it is the remodelling method where you can use still such a time you could point to the experience which is interest very. The chestnut of the writer of the magazine we appreciate in courage and search heart of the palm. The picture the heat sink of rather large texture (the Alfa25mm) with the FAN (the SANYO32mm) attaching, is the liberal BH6 and remodelling place.







Zgodovina sprememb…

  • spremenilo: OwcA ()

TribesMan ::

Pa owca ti si car. Glih neki tazga sm isku pa še prev za mojo plato je opisan. Najlepša ti dala (če ti še ni)! Bom mal preštudiral pol se pa kej javim.

LP
TribesMan
Moj kompjuter dela: KVIIIIK ... KVIIIK ... KVIIIK.

Ko ga navijem dela: KVIKKVIKKIVKKVIK. :)

TribesMan ::

Ja zelo uredu sam to je na žalost samo za PCI.
Kaj je z AGPjem tukej neki piše o tem da je to odvisno od grafične kartice, kaj misli s tem povedat? Ker je čudno. še enkrat sem pregledal datasheete pa res ni nič napisan o AGP frekvencah, zgleda da to ureja grafična al pa mogoče sam chipset?? Ker zadnjič ko sem probaval Radeona 9000PRO mi je na 124MHz vodilu (83MHz AGP) povzročal artefakte medtem ko jih pri 1112 MHz ni bilo in bi si želel imeti konstatno frekvenco AGPja.

Pa še zmer ne vem ali je nujno da sta frekvenca vodila CPUja in RAMa enaki in sinhronizirani ali je to tako kot pri novejših platah ko lahko vsako določiš posebej, to se previ nesinhrono?

Uno foro z zamenjavo kristala sem pa tud že jest probal sam je tako kot so napisal prehitra ura, ne dela USB, poleg vsega mi je pa takrat še kontroler za FDD crknil, ki ga pa itaq sploh nč ne rabm (Hvala bogu za pekače :) )

Vsi z novimi idejami na plano!!

Pa še enkrat hvala OwcA.

LP TribesMan
Moj kompjuter dela: KVIIIIK ... KVIIIK ... KVIIIK.

Ko ga navijem dela: KVIKKVIKKIVKKVIK. :)

Spajky ::

Če bi si skinil datasheet za BX chipset, bi ugotovil, da ima za AGP referenčni vhod za frekvenco na enem pinu, ki je zvezan z enim drugim, ki mu daje 66MHz; mislim, da bi bilo treba tu prekinit in mu injecirat konstantno 66MHz pa bi IMHO blo; jest sem o nečem podobnem razmišljal pred časom...8-)
"Bluzim na forumu, torej sem !" (še živ ) ...

TribesMan ::

Hvala za opozorilo Spajky, že kopljem po datasheetu. :))

LP

TribesMan
Moj kompjuter dela: KVIIIIK ... KVIIIK ... KVIIIK.

Ko ga navijem dela: KVIKKVIKKIVKKVIK. :)

TribesMan ::

Ja kot sem pričakoval uro AGPja regulira chipset. DAMN! Sicer ostaja še nekaj upanja da bi se dalo zadevo pohackat, namreč zadeva deluje nekako tako da generira uro, ki jo nato pošilja grafični in še samemu sebi. Izgleda tako kot da sploh ni notranje povezave in chipset "ne ve" kakšno uro generira. Tako da mogoče bi se dalo zadevo vsiliti, itaq pa AGP clock ni tak problem kot PCI.

Podobno pa je tudi z RAMom, na moji plati je sicer čip ki kontrolira RAM ločen od Clock generatorja na novejšig clock generatorjih pa je zadeva v enem kosu, vendar pa signal za uro RAMa v vsakem primeru prihaja iz chipseta in se podobno kot pri AGPju "vrne" nazaj v chipset. Tako da spreminjat te zadeve ni tako lahko kot zgleda. Sem že razmišljal da bi probal spremeniti uro samo FSBja tako da bi jo generiral ročno in ne iz BIOSa v BIOSu pa bi nastavil recimo 100MHz vodilo in potem bi ble vse ure po specifikaciji.
Sam bi znal bit problem če ne bi imel dovolj kvalitetnega čipa (narejenega za tako visoke frekvence), ker potem bi bil urin signal vse kaj drugega kot pa pravokotni signal.

LP TribesMan
Moj kompjuter dela: KVIIIIK ... KVIIIK ... KVIIIK.

Ko ga navijem dela: KVIKKVIKKIVKKVIK. :)


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