AMD ZEN - nova X86 Jedra

pegasus je 11. maj 2015 ob 12:15 izjavil:

IEEE fp standarda ti tega ne zagotavljata. Pravzaprav je znano, da na različnih implementacijah IEEE dobiš iz iste kode različne rezultate.
HW implementacija je predstavljena v knjigi in je mnogo enostavnejša kot IEEE.

juanrga:
AMD itself expect a commercial ready chip for 2020--2023, but yes, some pessimistic schedules extend to 2025.

https://community.amd.com/comm...

It is not needed to read the IEEE paper to see the mistakes here. Someone with minimum knowledge of HPC and technology development knows that no company will release an exascale chip in 2016--2017, because is technically impossible. However, the author is notorious by still believing that Xeon KNL Phi are "coprocessors", despite I explained him directly that the CPU version works in standalone mode.

But it could be poor. At least this author did count correctly the number of CPU cores in the EHP diagram: 32 cores. People at bitsandchips and at Fudzlilla claim that EHP has 16 cores. They cannot even count those little green boxes!!!!!

juanrga

Unfortunately, some new sites are confounding the "EHP" (Exascale Heterogenenous Processor) described in the recent IEEE paper by AMD engineers with the "server APU" announced by AMD's Papermaster at FAD 2015.

EHP is an exascale-level concept that targets the year 2020 (according to pesimistic schedules exascale not will be achieved before the year 2025). Whereas the "server APU" that appears in AMD roadmap targets the year 2017. This server APU includes 16 Zen cores, Greenland GPU, HBM2,...

Since the author confounds both chips, he mixes different technologies and makes incorrect claims about EHP. Some corrections:

(1) EHP doesn't use HBM2, because HBM2 doesn't provide the required bandwidth of 4TB/s needed for exascale requirements.

(2) EHP doesn't use Zen cores, neither is using Zen+ cores. EHP uses some future not defined core and, in fact, AMD engineers claim that they didn't decide if the cores will be x86 or ARM.

(3) EHP doesn't have a Greenland GPU, but a future unnamed architecture.

(4) EHP doesn't use DDR4 channels. AMD engineers make it clear on the paper that the memory architecture is dual with 3D-RAM plus NVRAM.

(5) The target process node is not 14nm.

(6) EHP is a concept and doesn't appear in any roadmap.

There are more confusions and issues, but the above list is enough to understand that EHP described by AMD in the paper is completely different to what is being said here. Now, after spending some time on the comments, I see a lot of ignorance about exascale level stuff and will do some additional remarks:

(a) Many companies are designing exascale level chips: IBM, Fujitsu, Nvidia, Intel...

(b) AMD's EHP isn't anything special when compared to exascale-level designs from others companies. The chip that is more similar to AMD's EHP is from Nvidia, because Nvidia also proposes an APU that they name "HCN" (Heterogenenous Compute Node). I will give some few details about the HCN made by Nvidia engineers just for people can compare with AMD's EHP.

The exascale chip proposed by Nvidia hits 20 TFLOPS of double precision, uses 16 high-performance ARM cores, and has 256GB 3D-DRAM on chip, backed up by 512GB NVRAM (PCM). The TDP of the chip is 230W and targets the 7nm node with a die size of 650mm?. CPU and GPU cores are 'fused' on a 2D-interconnect.

hojnikb je 30. apr 2015 ob 20:22 izjavil:

Recimo določen software, ko je skompajlan z intel c++ kompilerjem, dela bolš, če pofejkaš procesorid na intel. Ker če zazna amd, laufa manj efektivno kod, ker Intel pač ne optimizira svojih kompilerjov za druga ko svojo robo.

hojnikb je 6. avg 2015 ob 17:33 izjavil:

Dovolj je ~170e za najcenejšo i5 pa si dober do konc desetletja. Pri amd pa morš cincat pr vsaki igri, če je optimizirana za več jeder. Marsikater špil namreč ni in amd kolcne, i3 pa pride naprej...

tiborrr je 6. avg 2015 ob 21:55 izjavil:

Zdaj ne vem, ali se delaš trapastega ali ti pa res niso jasna načela rentabilnosti nekega projekta. Kakorkoli že - prvi Zen bo itak Opteron, t.j. po vsej verjetnosti ~ 2000-pinski čip, tako kot je trenutni G34 in LGA-2011-3 in bo sestavljen iz dveh nodeov. Torej, prvo HPC, vse ostalo bo spet sekundarno. Ker ni resursov za vse. Torej ja, 'niša'.

tiborrr je 6. avg 2015 ob 21:34 izjavil:

hojnikb je 6. avg 2015 ob 20:23 izjavil:

> in v tem je AMD pač kralj p/p :)

AMD že dolgo ni več p/p

No ja. Moj 4P Opteron 6344 (4x12c) sistem, ki je stal manj kot tri jurje, je v CFDju hitrejši od 15 jurjev težke Haswell-EP kripe. CMT je super zadeva, če veš, zakaj jo rabiti. Bulldozer je arhitektura, ki je v ta svet prinesla ogromno za malo denarja.

tiborrr je 6. avg 2015 ob 21:38 izjavil:

To ni niša, to je poleg konzol največji trg (server, hpc). Ali res misliš, da bi AMD šel v dizajn Bulldozerja zato, ker pač nimajo pojma ali ker so imeli denarja le za eno platformo in so se odločili za najbolj profitabilno?

Isotropic je 7. avg 2015 ob 10:21 izjavil:

koliko stane pa abaqus, kaj veš?
pa kuk licenc ansysa bi rabili / stane 30k?
slišal sem edino, da so edu licence par 100e na jedro.

pa daj pokaži kakšno lepo slikico

tiborrr je 7. avg 2015 ob 09:51 izjavil:

Navsezadnje je v CFX FX-8150 približno ~ 40% hitrejši od i7-4770K